Electronic memories comprising arrays of memory cells arranged in rows and columns are well known. Most such memories are capable of storing a single bit of data in each memory cell. For speed, reliability, and robustness in a noisy and un-predictable environment, complementary dual bit lines cells are used to store the true and complementary data at the same time, where normally just one of the single cell is enough to store the data; e.g. 2T2C FeRAM cell, 3T2C Trinion FeRAM, 2T2C DRAM cell, 2T2C dynamic register cell, etc. Each of these 2C or 2R type dual bit lines cells has two binary storage elements and is normally equivalent to or can be used as two regular single cells. It seems a little wasteful since each storage element is only for storing one-half bit of the data, when a normal single cell would store one full bit of data.
Since the 2C or 2R type cells have two binary storage elements, they can each have four logic states, “00”, “01”, “10” and “11”, and could represent two bits of data. Currently, only the “01” and “10” states are used to represent a robust Logic-0 and Logic-1 for a data bit. An improvement in the art would be obtained if these 2C or 2R type and dual bit lines robust cells could use the currently un-used states “00” and “11” to store more than just one bit of data, with some tolerable compromise on noise margin, and each storage element could store more than one-half bit of data. Having the choice to select bit width usage for a dual bit lines dual storage elements cell can be a yield improvement function for the specific memory.